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TECHNICAL DATA
IW4027B
Dual JK Flip-Flop
The IW4027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and transferred to the output on the positive-going edge of the Clock. The active HIGH asynchronous Reset and Set are independent and override the J, K, or Clock inputs. The outputs are buffered for best system performance. * Operating Voltage Range: 3.0 to 18 V * Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25C * Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply
ORDERING INFORMATION IW4027BN Plastic IW4027BD SOIC TA = -55 to 125 C for all packages
PIN ASSIGNMENT LOGIC DIAGRAM
FUNCTION TABLE
Inputs Set Reset Clock L H H H L H L L L L X X X J X X X L H L H K X X X L L H H Outputs Qn+1 L H H H L Qn Qn+1 H L H L H Qn
w
w
w
.d
sh ta a
ee
u. t4
om c
PIN 16 =VCC PIN 8 = GND
L L L L
No change
X = don't care Qn+1 = State After Clock Positive Transition
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IW4027B
MAXIMUM RATINGS*
Symbol VCC VIN IIN PD Ptot Tstg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP, SOIC Package Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +20 -0.5 to VCC +0.5 10 500** 100 -65 to +150 260
Unit V V mA mW mW C C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. **Derating: - Plastic DIP from -55 to +100C - SOIC Package from -55 to +65C - Plastic DIP: - 10 mW/C from +100 to +125C - SOIC Package: : - 7 mW/C from +65 to +125C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Operating Temperature, All Package Types Min 3.0 0 -55 Max 18 VCC +125 Unit V V C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this should be constrained to the range high-impedance circuit. For proper operation VIN GNDVIN VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
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IW4027B
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low Level Input Voltage Minimum High-Level Output Voltage Test Conditions VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V VIN=GND or VCC V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 18 5.0 10 15 20 5.0 10 15 5.0 5.0 10 15 Guaranteed Limit -55C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 4.5 9.0 13.5 0.05 0.05 0.05 0.5 1.0 1.5 0.1 1.0 2.0 4.0 20 0.64 1.6 4.2 -0.64 -2.0 -1.6 -4.2 25C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 4.5 9.0 13.5 0.05 0.05 0.05 0.5 1.0 1.5 0.1 1.0 2.0 4.0 20 0.51 1.3 3.4 -0.51 -1.6 -1.3 -3.4 125 C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 4.5 9.0 13.5 0.05 0.05 0.05 0.5 1.0 1.5 1.0 30 60 120 600 0.36 0.9 2.4 mA -0.36 -1.15 -0.9 -2.4 Unit V
VIL
V
VOH
V
VIL=1.5V, VIH=3.5V, IO=-1A VIL=3.0V, VIH=7.0V, IO=-1A VIL=4.0V, VIH=11V, IO=-1A VOL Maximum Low-Level Output Voltage VIN=GND or VCC
V
VIL=1.5V, VIH=3.5V, IO=1A VIL=3.0V, VIH=7.0V, IO=1A VIL=4.0V, VIH=11V, IO=1A IIN ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Minimum Output Low (Sink) Current VIN= GND or VCC VIN= GND or VCC
A A
IOL
VIN= GND or VCC VOL=0.4 V VOL=0.5 V VOL=1.5 V
mA
IOH
Minimum Output VIN= GND or VCC High (Source) Current VOH=4.6 V VOH=2.5 V VOH=9.5 V VOH=13.5 V
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IW4027B
AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200 k, Input tr=tf=20 ns)
VCC Symbol fmax Parameter Maximum Clock Frequency V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 3.5 8 12 300 130 90 300 130 90 400 170 120 200 100 80 Guaranteed Limit -55C 25C 3.5 8 12 300 130 90 300 130 90 400 170 120 200 100 80 7.5 125C 1.75 4 6 600 260 180 600 260 180 800 340 240 400 200 160 Unit MHz
tPLH, tPHL
Maximum Propagation Delay, Clock to Q or Q
ns
tPLH
Maximum Propagation Delay, Set to Q or Reset to Q Maximum Propagation Delay, Set to Q or Reset to Q Maximum Output Transition Time, Any Output
ns
tPHL
ns
tTLH, tTHL
ns
CIN
Maximum Input Capacitance
pF
TIMING REQUIREMENTS (CL=50pF, RL=200 k, Input tr=tf=20 ns)
VCC Symbol tw Parameter Minimum Pulse Width, Clock V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 140 60 40 180 80 50 200 75 50 45 5 2 Guaranteed Limit -55C 25C 140 60 40 180 80 50 200 75 50 45 5 2 125C 280 120 80 360 160 100 400 150 100 90 10 4 Unit ns
tw
Minimum Pulse Width, Set or Reset
ns
tsu
Minimum Data Setup Time
ns
tr, tf
Maximum Input Rise or Fall Time, Clock
s
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IW4027B
VCC K(J)
0.5
tSU
0.9 0.9 0.5 0.1
0V VCC
CLOCK
0.5 0.1
tLH tW
tHL
0V
VOHCC Q(Q)
0.5VCC
VOL tREM tPHL(tPLH) VCC SET (RESET)
0.5
0V
VCC ASET nQ(nQ) uoia (RESET)
0V VCC
RESET (SET)
0.5
tW2 0.9 Q(Q) 0.5VCC 0.1 tTHL(tTLH) tPHL(tPLH) Figure 1. Switching Waveforms
0V VOHCC UDD UOL
0V
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IW4027B
N SUFFIX PLASTIC (MS - 001BB)
A 16 9 B 1 8
Dimensions, mm Symbol A B MIN 18.67 6.10 0.36 1.14 2.54 7.62 0 2.92 7.62 0.20 0.38 10 3.81 8.26 0.36 MAX 19.69 7.11 5.33 0.56 1.78
F
L
C D F
C -T- SEATING
PLANE
N G D 0.25 (0.010) M T K M H J
G H J K L M N
NOTES: 1. imensions "A", "B" do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side.
D SUFFIX SOIC (MS - 012AC)
A 16 9
Dimensions, mm Symbol. MIN 9.80 3.80 1.35 0.33 0.40 1.27 5.72 0 0.10 0.19 5.80 0.25 8 0.25 0.25 6.20 0.50 MAX 10.0 4.00 1.75 0.51 1.27
B P
H
A B C
C R x 45
1
G
8
D F G
-TD 0.25 (0.010) M T C M K
SEATING PLANE
J
F
M
H J K M P R
NOTES: 1.Dimensions A and B do not include mold flash or protrusion. 2.Maximum mold flash or protrusion 0.15 mm (0.006) per side for A, for B - 0.25 mm (0.010) per side.
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